1. Technical Field
The present invention relates to computer system memory management utilizing multiplexed input and output of data to system memory to provide for high speed data throughput, and more particularly to reducing delay or system latency by eliminating the need for data buffering devices or systems to handle the throughput of data into and out of system memory.
2. Description of the Related Art
A typical computer system consists of a number of modules or components. Computer systems typically include a central processing unit (CPU) such as a microprocessor which functions with memory storage components to interface with both one or more CPU""s and a variety of input output (I/O) components for connecting external devices to the microprocessor which provide data for processing by the system. These storage components may be read only memory (ROM), random access memory (RAM) most typically used for system memory, or any other suitable storage means. A computer system typically also includes special purpose components, such as memory management units, co-processors, and other ancillary subsystems used to enhance the operation of the main system components as part of the computer system. The memory component of a computer system, also known as xe2x80x9cmain memory,xe2x80x9d is a system resource that is dynamically allocated to programs or processes. Main memory is typically dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM). Processor main memory is usually xe2x80x9cbytexe2x80x9d organized. That is, memory is arranged as a sequence of 8-bit bytes and the byte is the smallest unit of information accessed out of the memory. In early conventions, an entire row is selected by a row address and columns and accessed in groups of 8 bits. In current design implementations, 64-bit or 128-bit words are accessed at one time in terms of memory management Utilizing commonly applied error correction coding (ECC) of eight additional bits to a 64-bit data word or line, memory storage and management designs are now using data lines of a total of 144-bits (two 64-bit words) in handling system operations within a processor or multiprocessor system. The invention disclosed most particularly relates to microprocessor computer system cache memory or memory subsystems which utilize registers for short-term storage of information necessary to operate within the system as a whole.
Much of the prior art in the field of computer system memory management addresses how to maximize the data throughput, and increase processing speed, into and out of memory register arrays used in a variety of different computer systems. U.S. Pat. No. 5,313,624 issued to Harriman describes the use of a multiplexor to route data to one of four memory arrays. U.S. Pat. No. 4,835,738 issued to Niehaus discloses a computer memory array interfaced to a data register through a multiplexor. While these references teach the use of computer architecture and logic design to allow continuous data flow to multiple paths simultaneously, they do not teach the multiplexing function that distributes data to several different memory array portions of a devices total memory with continuous data flow.
The present invention provides a method and apparatus for avoiding the complexity of random access memory (RAM) with eight input and/or output ports by utilizing a multiplexing method to reduce the number of required ports to two while maintaining throughput speed and path accessability to all memory arrays provided in the computer system. A logic structure which can receive and store a continuous flow of data items from multiple data paths simultaneously is disclosed. The structure permits low latency simultaneous retrieval of previously stored data items by multiple destinations.
A system of the invention utilizes two or more memory registers in the form of register arrays coupled to a first multiplexor for receiving data from a data source such as a microprocessor coupled to said memory registers. A second multiplexor is coupled to the memory registers for outputting data from the memory registers to the system. The registers are configured as slices of arrays, each slice having two independent inputs coupled to the first multiplexor to receive data input Each slice has two independent outputs to convey data to the second multiplexor. The system includes means to track the identification and location of data being stored to the registers from the first multiplexor as well as means to select identified data within the register arrays to allow output of the data to the second multiplexor in a controlled manner.
The invention also provides a method of handling data between a central processing unit (CPU) and a data storage means in which the data storage means receives and stores a continuous flow of data items being processed in the CPU in which data items are received from multiple sources simultaneously comprised of a plurality of memory registers configured into an array of slices of memory, each slice having two input ports coupled to an input multiplexor means and two output ports coupled to an output multiplexor means. The method: provides data words from a CPU to a first multiplexor interface coupled to the CPU and memory; identifies and tracks each of the data words; stores the data words sequentially in each slice of memory and storing the location and identification of each data word stored; and then outputs the data words to a destination requested by the CPU by identifying and selecting the slice containing the start of the requested data and sequentially reading the data words requested.
Apparatus of the invention comprises first and second memories, each having an input for writing data into the memory and an output for reading the data from the memory. A first input multiplexor has multiple system inputs for receiving the data, and an output coupled to the input of the first memory. Similarly a second input multiplexor has multiple system inputs for receiving the data simultaneously with the first input multiplexors receiving the data, and an output coupled to the input of the second memory. An output multiplexor has inputs coupled to the outputs of the first and second memories. An input controller identifies and locates the data in the memories, and an output controller coupled to the output multiplexor responds to that identification and location of the data.
Other features and advantages of the invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.